Banga, India
DIGITAL DESIGN TRAINING
Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies Clock domain crossing Reset Power management in SOC State machines Register Memories Synthesis Predict design output Gate level simulations Debugging incorrect designs Clock distribution Active low and active high PISO, SIPO Comparator Designing circuits for various requirements CRC calculation logic ...
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